1. Field of the Invention
This invention relates to testing apparatus and methods of operation. More particularly, the invention relates to apparatus and methods for testing microprocessor chips using scan strings.
2. Description of Prior Art
Testing operations for microprocessor chips usually require the chip to go from a perfectly idle state, where all the clocks, both functional and scanned are completely off, to a state where the scanned clocks are turned on for scanning. This is normally what happens every time a test or service processor is to read or write the state of the chip internal logic. Since the scan clocks affect every scannable latch element on a chip (and in some cases every dynamic circuit if the scan clock is also shared as a system clock), the node toggle activity of the chip can easily reach the 50 percent mark where, in that mode, a 0.5 probability exists that a typical node would toggle or switch to an active state. It is not very unusual that the percentage of node toggling can be very much higher than 50 percent (as compared to a typical 20 percent node toggle activity when the chip is running functional code). All of this leads to a higher than average current spikes in the chip, especially when the first scan clock is going active immediately after the chip has been in the idle state (clocks off). In some cases, the inability of the power supply to compensate for the sudden drop in voltage within an appropriate time window, can lead to the chip voltage dropping below a threshold level beyond which the storage elements and dynamic circuits in the chip can lose their storage states.
Another problem encountered is storing test data received by a test or service processor from the chip under test. Every time the chip is read, memory space must be allocated to store the state of the chip latches. The time to access the state of a chip can also be prohibitive since all scan strings on the chip must be connected into a super long scan string accessible by the test processor through a Joint Test Action Group (JTAG) or JTAG/IEEE 1149.1 test port.
Still another problem is broken long scan strings in the testing of microprocessor chips. Design verification of the test function requires that long scan strings be perfectly connected together. When a long scan string is broken design verification is delayed until the scan string is connected together.
Accordingly, a test apparatus and method which overcomes the foregoing problems will advance the state of the art in testing microprocessor chips.
The prior art related to testing integrated chips is as follows:
U.S. Pat. No. 4,503,537 issued Mar. 5, 1985, discloses a parallel path self-testing system for a circuit module. Test chips in the module contain switching circuits to connect scan paths of the chips in parallels between different stages of a random signal generator and a data compression means. The switching circuits also disconnect scan paths from a signal generator and data compression circuitry and arrange the circuits in a single scan path to perform testing.
U.S. Pat. No. 4,597,042 issued Jun. 24, 1986, discloses a device for selectively loading data in and reading data out of latch strings located in irreplaceable units containing the circuitry of a data processing system realized in accordance with Level Scan Sensitive Design (LSSD) technique. Data to be loaded and read out of a latch string is propagated in a data loop under control of an addressing circuit.
U.S. Pat. No. 4,872,169 issued Oct. 3, 1989, discloses testing circuitry which consists of a series of shift registers or latches which form a serial scan path through a logic circuit. The scan path is used to observe and control logic elements in the design by a serial scan operation. The scan path can be compressed or expanded so that the scan path only passes through a desired logic element to be tested. Devices connected on a scan path can be selected or deselected allowing the serial path to either flow through or by-pass a given logic circuit's internal scan path.
U.S. Pat. No. 4,897,837 issued Jan. 30, 1990, discloses a plurality of shift registers connected in series between an input terminal for inputting test patterns and an output terminal for outputting the signal as a result of the test operations. The test pattern signals are shifted by the shift registers to apply corresponding test patterns to each of the circuit portions. The result of each of the circuit portions is taken into a shift register and shifted to the direction of the output terminal. A by-pass circuit applies a test pattern signal from the input directly to the prescribed shift register and not through the other shift registers on the way to the circuit on test.
U.S. Pat. No. 5,233,612 issued Aug. 3, 1993, discloses a test device for an integrated chip including a first processor, the test device including interface means for interfacing the first processor with other circuits and a second processor coupled to the first processor as an emulator. The interface means includes a scan path constituted by a string of first cells and including serially connected buffer means able to latch data normally transferred between the processor means and the circuit. A comparator compares data in a scan path from the second processor with data received in a second scan path from the first processor.
U.S. Pat. No. 5,253,255 issued Oct. 12, 1993, discloses a method of debugging the operation of an integrated circuit chip by loading a shift register in parallel with data from internal test points thereby taking a snapshot of the internal state of a chip at a desired clock cycle. The data is then shifted out of the shift register serially, one bit per clock. The data is displayed in a usable form on a computer display. The process is repeated by looping back to the beginning of the test to take a snapshot one clock later than the previous test capture point.
U.S. Pat. No. 5,325,368 issued Jun. 28, 1994, discloses a test bus incorporated into a computer system including a plurality of components, each component in turn including boundary scan architecture for testing the components by the test bus. Non-volatile memory is coupled to the test bus to store boundary scan information for each of the components in the non-volatile memory. The non-volatile memory is accessed to retrieve boundary scan information required by the test bus for testing the component.
U.S. Pat. No. 5,42,644 issued Aug. 15, 1995 discloses a universal multiple interconnect sensing module capable of sensing a very large number of interconnection points and equipment under test. The universal module includes a transmitter/receiver for each interconnection point. An address generator coupled to the transmitter/receiver generates an address signal at a unique time period. Logic control circuits coupled to the output of each receiver sense the state of the receiver at each individual unique address time. The control circuits constrain the information received from the receiver and generate an output coupled to an encoder which generates information indicative of all interconnections, opens and grounds in the equipment under test during each unique time period.
U.S. Pat. No. 5,491,666 issued Feb. 13, 1996, and having an effective filing date of Mar. 10, 1994, discloses apparatus and a method for allowing separate portions of an integrated circuit to be individually tested and otherwise manipulated and configured. The apparatus utilizes boundary scan or similar shift register circuitry without affecting operations in other circuits and other sections of the integrated circuits. A plurality of individual boundary scan or similar shift register circuits are associated with separate portions of the circuitry of the integrated circuit. The registers of the individual boundary scan circuits are joined to provide a series boundary scan register chain with a plurality of individual controllers within an integrated circuit so that individual portions of the circuity included within the integrated circuit may be individually manipulated.
U.S. Pat. No. 5,495,487 issued Feb. 27, 1996, and having an effective filing of Sep. 7, 1988, discloses a boundary scan test system which provides partitioning devices, such as registers, latches, transceivers and buffers, with boundary scan testability to provide observation and control of input to and from combinatorial logic which does not have boundary scan testability.
U.S. Pat. No. 5,515,505 issued May 7, 1996, and having a filing date of Nov. 4, 1994, discloses a semi-conductor integrated circuit with a boundary scan circuit composed of logic circuits having different logic levels. A plurality of serially connected test circuits are connected between the logic circuits and input and output pins. The serially connected test circuits include a first group of test circuits having the same logic level as those of the input/output pins. The test circuits of the first group are connected directly in series to each other. A second group of test circuits having logic levels different from those of the input pins are connected to a plurality of level converters for converting logic levels. The test circuits of the second group are connected through the level converters to the input/output pins.
None of the prior art discloses or suggests individually manipulated scan strings of a plurality of integrated circuits to reduce excessive voltage drop in a circuit; memory allocations for test results; scan time, and loss of access to chip internals due to a break in a Long Shift Register Latch (LSRL) scan.